Linear sum codes for random access memories

Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...

Static Random Access Memories

Testing static random access memories (SRAM’s) for all possible failures is not feasible. We have to restrict the class of faults to he considered. This restricted class is called a fault model. A fault model for SRAM’s is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms are proposed, that cover 100% of the fa...

Linear codes for the sum mod-2 multiple-access channel with restricted access

Random Access to Fibonacci Codes

A Wavelet tree allows direct access to the underlying file, resulting in the fact that the compressed file is not needed any more. We adapt, in this paper, the Wavelet tree to Fibonacci Codes, so that in addition to supporting direct access to the Fibonacci encoded file, we also increase the compression savings when compared to the original Fibonacci compressed file.

Emerging Technologies in Random Access Memories

Memories based on charge storage principle are used since many decades. The greater speed and higher density of memory chips are now achieved at lower costs. However, speed and size are gradually approaching the physical limits. Newer memory concepts are therefore being explored. This paper presents a discussion on different random access memories based on new concepts. An overview of emerging ...